For example, Japanese Patent Laid-open Nos. 7-283280, 8-50146 (corresponding to international publication WO 95/34000), 8-201427, 11-23615 (corresponding to U.S. Pat. No. 6,305,230), 2001-159643, 10-308423, 11-97471 (corresponding to European Patent No. EP 1022775), and 2000-150594 (corresponding to European Patent No. EP 0999451) disclose a structure of a prober having a probe (contact terminal) formed using a technique of fabricating a semiconductor integrated circuit device, an insulating film, and lead lines, a method of fabricating the prober, and a technique of enabling practice of a probe test even for a chip having test pads with a reduced pitch by using the prober.
Japanese Patent Laid-open No. 2002-163900 (corresponding to U.S. patent Application Publication No. US 2002/061606, published at May, 23, 2002) discloses a technique that enables omission of the probe test to bad chips by performing the probe test only to chips determined as good chips in wafer level burn-in.
Japanese Patent Laid-open No. 5-74888 discloses a technique that enables omission of the probe test to the chips determined as bad chips by excluding chips determined as bad chips in a chip appearance test from an object of a characteristic test, and performing the characteristic test to only chips determined as good chips in the appearance test.
Japanese Patent Laid-open No. 7-94559 discloses a technique in which chips on a wafer added with a bad mark by image processing are subjected to an electrical characteristic test while being not contacted with a probe needle, thereby the probe test can be omitted to bad chips.
Japanese Patent Laid-open No. 7-142547 discloses a technique that enables reduction in total test time by detecting bad chips on a wafer by a chip appearance tester, and furthermore specifying bad chips that were not relieved, and omitting the test to the specified bad chips.
Japanese Patent Laid-open No. 7-147304 (corresponding to U.S. Pat. No. 5,644,245) discloses a technique that enables prevention of production of bad chips due to a needle mark trouble, by performing a probe test to subsequent chips when a needle mark of a probe needle is within tolerance, and omitting the probe test when the needle mark is out of tolerance.
Japanese Patent Laid-open No. 5-3239 discloses a technique that enables omission of formation of unnecessary bump electrodes by performing the a probe test while excluding chips in a peripheral region of a wafer where bad chips produced in a wafer processing process from an object of the probe test, then omitting formation of bump electrodes on the chips in the peripheral region of the wafer.
Japanese Patent Laid-open No. 8-306748 discloses a technique that enables improvement in throughput of the probe test by first performing the probe test to all elements on a wafer, then performing remedy, and then performing a second probe test to elements except for unrelievable elements.
Japanese Patent Laid-open No. 6-089929 discloses a technique that incorporates an electrically writable, permanent recording unit for each of chips in a wafer, so that tests are performed to only robust chips after certain chips were determined as bad chips in a result of a certain test.